Electronic circuit systems are well known for their ability to rapidly transfer information. These systems are generally comprised of a series of data storage units, a data bus, an address bus, and a control line. The information contained on the address bus specifies which storage unit the circuitry should access to write or read the data. Whether the data is read or written is controlled by the voltage on the read/write control line, e.g., if a high voltage indicates a read operation, a low voltage would indicate a write operation. If the circuit is conducting a read operation, the circuitry reads the data from the addressed storage unit onto the data bus. On the other hand, if the circuit is conducting a write operation, the circuitry writes the data on the data bus into the addressed storage unit.
Typically, a storage unit consists of (1) a data register and (2) an address decoder. This type of architecture is highly efficient in transferring data, but in some circumstances, may introduce data errors. For example, if the circuit attempts to transfer information too rapidly, the circuit may read or write erroneous data. Erroneous data may be read or written if the circuitry attempts to write or read data before the address lines have properly stabilized. When this occurs, data may be written from or read to the wrong location. Errors of this type may be very serious, e.g., the circuitry may accidentally overwrite an important piece of data or use an incorrect value in a calculation.
One method of solving this problem is to reserve an address for use as a signal that the address on the address bus has stabilized. Reserving an address in this fashion obviously eliminates the number of addresses that can actually be used to address storage units, e.g., where the address bus is formed by n lines, only 2n-1 registers may be addressed. Generally, the address reserved will be either all "1s" or all "0s." The reserved address is commonly referred to as the precharge address.
When the circuitry drives precharge address onto the address line, the system is in a precharge state. When in this state, the circuitry does not allow the storage units to be read from or written to. To utilize the precharge addressing technique, the circuit must contain (1) a precharge logic capable of precharging the address bus to the precharge address and (2) a precharge sensor capable of checking for the precharge state on the address bus.
The precharge logic and the precharge sensor operate to eliminate address decoding errors by delaying all reading or writing until the address bus has had time to stabilize. The precharge sensor will only enable the address decoders once it senses that the precharge logic has released the address lines from the precharge state. Moreover, the sensor will only enable the decoders after a delay time greater than or equal to the address bus stabilization time. As a result, data is read or written only to the properly addressed register. It is important to arrange the precharge sensor at the extremity of the address bus so as to ensure maximum delay, so that the address is stable when the precharge sensor changes state.
A fundamental drawback to the architecture of the prior art is that it generally requires the use of master-slave flip-flops as registers in the storage units. The prior art required master-slave flip-flops because they transfer a datum only on the rising or falling edge of the switching impulse. By transferring datum only on the edges of a switching impulse, master-slave flip-flops ensure that data is not lost if the input datum changed while the switching impulse was active. However, master-slave flip-flops are larger in size and consume more power than gate-controlled single-stage flip-flops. As a result, they are not as economical as single-stage flip-flops.
Functionally, single-stage flip-flops differ from master-slave flip-flops by responding to changes in the state of an input datum whenever the switching impulse is active. Thus, if the datum changes before the end of the switching impulse, the flip-flop's output will change state and the original datum will be lost before being stored.
To overcome this problem, the prior art teaches the use of a specific suitably-timed switching or gating signal. The gating signal is obtained as the logic combination of the output of the precharge sensor with the clock signal that enables the datum switchings. A clock signal changes state roughly half-way through the time of duration of the datum. Therefore, the gating signal ends before the new datum switching operation begins. Because the gating signal controls the actual storing of the datum, the datum will not be lost even if the circuitry uses a single-step flip-flop.
The drawback of this solution is that it requires the use of an additional gating signal: A gating signal that may not be immediately available, and, in any event, increases the system's consumption of power.
Furthermore, designing proper timing of the gating signal requires a detailed knowledge of the behavior of the specific components of the system, e.g., bus delays, decoding delays, etc. The resulting circuitry is inelastic because it is dependent on the specific delay times of the particular components used. This serves as an extreme handicap to circuit designers. This handicap stems from production concern. Circuit manufacturers like to rely on obtaining similar components from two or more sources in order to remain flexible in what may be unpredictable business markets. However, components from different sources, although functionally similar, may have substantially different delay times. As a result, a designer must calculate the minimum length of the gating impulse based on the slowest possible combination of components. Consequently, the speed of the system is unduly hampered except when operating under the worst of all possible conditions.